|
|
@ -35,6 +35,8 @@ |
|
|
|
#define ARCH_CPU_X86_FAMILY 1 |
|
|
|
#elif defined(__ARMEL__) |
|
|
|
#define ARCH_CPU_ARM_FAMILY 1 |
|
|
|
#elif defined(__aarch64__) |
|
|
|
#define ARCH_CPU_ARM64_FAMILY 1 |
|
|
|
#elif defined(__ppc__) || defined(__powerpc__) || defined(__powerpc64__) |
|
|
|
#define ARCH_CPU_PPC_FAMILY 1 |
|
|
|
#endif |
|
|
@ -92,6 +94,13 @@ inline void MemoryBarrier() { |
|
|
|
} |
|
|
|
#define LEVELDB_HAVE_MEMORY_BARRIER |
|
|
|
|
|
|
|
// ARM64 |
|
|
|
#elif defined(ARCH_CPU_ARM64_FAMILY) |
|
|
|
inline void MemoryBarrier() { |
|
|
|
asm volatile("dmb sy" : : : "memory"); |
|
|
|
} |
|
|
|
#define LEVELDB_HAVE_MEMORY_BARRIER |
|
|
|
|
|
|
|
// PPC |
|
|
|
#elif defined(ARCH_CPU_PPC_FAMILY) && defined(__GNUC__) |
|
|
|
inline void MemoryBarrier() { |
|
|
@ -215,6 +224,7 @@ class AtomicPointer { |
|
|
|
#undef LEVELDB_HAVE_MEMORY_BARRIER |
|
|
|
#undef ARCH_CPU_X86_FAMILY |
|
|
|
#undef ARCH_CPU_ARM_FAMILY |
|
|
|
#undef ARCH_CPU_ARM64_FAMILY |
|
|
|
#undef ARCH_CPU_PPC_FAMILY |
|
|
|
|
|
|
|
} // namespace port |
|
|
|