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@ -35,6 +35,8 @@ |
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#define ARCH_CPU_X86_FAMILY 1 |
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#define ARCH_CPU_X86_FAMILY 1 |
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#elif defined(__ARMEL__) |
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#elif defined(__ARMEL__) |
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#define ARCH_CPU_ARM_FAMILY 1 |
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#define ARCH_CPU_ARM_FAMILY 1 |
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#elif defined(__aarch64__) |
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#define ARCH_CPU_ARM64_FAMILY 1 |
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#elif defined(__ppc__) || defined(__powerpc__) || defined(__powerpc64__) |
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#elif defined(__ppc__) || defined(__powerpc__) || defined(__powerpc64__) |
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#define ARCH_CPU_PPC_FAMILY 1 |
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#define ARCH_CPU_PPC_FAMILY 1 |
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#endif |
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#endif |
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@ -92,6 +94,13 @@ inline void MemoryBarrier() { |
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} |
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} |
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#define LEVELDB_HAVE_MEMORY_BARRIER |
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#define LEVELDB_HAVE_MEMORY_BARRIER |
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// ARM64 |
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#elif defined(ARCH_CPU_ARM64_FAMILY) |
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inline void MemoryBarrier() { |
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asm volatile("dmb sy" : : : "memory"); |
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} |
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#define LEVELDB_HAVE_MEMORY_BARRIER |
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// PPC |
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// PPC |
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#elif defined(ARCH_CPU_PPC_FAMILY) && defined(__GNUC__) |
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#elif defined(ARCH_CPU_PPC_FAMILY) && defined(__GNUC__) |
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inline void MemoryBarrier() { |
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inline void MemoryBarrier() { |
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@ -215,6 +224,7 @@ class AtomicPointer { |
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#undef LEVELDB_HAVE_MEMORY_BARRIER |
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#undef LEVELDB_HAVE_MEMORY_BARRIER |
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#undef ARCH_CPU_X86_FAMILY |
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#undef ARCH_CPU_X86_FAMILY |
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#undef ARCH_CPU_ARM_FAMILY |
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#undef ARCH_CPU_ARM_FAMILY |
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#undef ARCH_CPU_ARM64_FAMILY |
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#undef ARCH_CPU_PPC_FAMILY |
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#undef ARCH_CPU_PPC_FAMILY |
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} // namespace port |
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} // namespace port |
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