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@ -39,6 +39,8 @@ |
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#define ARCH_CPU_ARM64_FAMILY 1 |
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#define ARCH_CPU_ARM64_FAMILY 1 |
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#elif defined(__ppc__) || defined(__powerpc__) || defined(__powerpc64__) |
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#elif defined(__ppc__) || defined(__powerpc__) || defined(__powerpc64__) |
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#define ARCH_CPU_PPC_FAMILY 1 |
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#define ARCH_CPU_PPC_FAMILY 1 |
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#elif defined(__mips__) |
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#define ARCH_CPU_MIPS_FAMILY 1 |
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#endif |
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#endif |
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namespace leveldb { |
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namespace leveldb { |
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@ -110,6 +112,13 @@ inline void MemoryBarrier() { |
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} |
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} |
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#define LEVELDB_HAVE_MEMORY_BARRIER |
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#define LEVELDB_HAVE_MEMORY_BARRIER |
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// MIPS |
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#elif defined(ARCH_CPU_MIPS_FAMILY) && defined(__GNUC__) |
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inline void MemoryBarrier() { |
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__asm__ __volatile__("sync" : : : "memory"); |
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} |
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#define LEVELDB_HAVE_MEMORY_BARRIER |
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#endif |
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#endif |
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// AtomicPointer built using platform-specific MemoryBarrier() |
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// AtomicPointer built using platform-specific MemoryBarrier() |
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