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272 rader
12 KiB
272 rader
12 KiB
#ifndef __KERN_MM_MMU_H__
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#define __KERN_MM_MMU_H__
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/* Eflags register */
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#define FL_CF 0x00000001 // Carry Flag
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#define FL_PF 0x00000004 // Parity Flag
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#define FL_AF 0x00000010 // Auxiliary carry Flag
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#define FL_ZF 0x00000040 // Zero Flag
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#define FL_SF 0x00000080 // Sign Flag
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#define FL_TF 0x00000100 // Trap Flag
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#define FL_IF 0x00000200 // Interrupt Flag
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#define FL_DF 0x00000400 // Direction Flag
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#define FL_OF 0x00000800 // Overflow Flag
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#define FL_IOPL_MASK 0x00003000 // I/O Privilege Level bitmask
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#define FL_IOPL_0 0x00000000 // IOPL == 0
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#define FL_IOPL_1 0x00001000 // IOPL == 1
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#define FL_IOPL_2 0x00002000 // IOPL == 2
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#define FL_IOPL_3 0x00003000 // IOPL == 3
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#define FL_NT 0x00004000 // Nested Task
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#define FL_RF 0x00010000 // Resume Flag
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#define FL_VM 0x00020000 // Virtual 8086 mode
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#define FL_AC 0x00040000 // Alignment Check
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#define FL_VIF 0x00080000 // Virtual Interrupt Flag
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#define FL_VIP 0x00100000 // Virtual Interrupt Pending
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#define FL_ID 0x00200000 // ID flag
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/* Application segment type bits */
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#define STA_X 0x8 // Executable segment
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#define STA_E 0x4 // Expand down (non-executable segments)
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#define STA_C 0x4 // Conforming code segment (executable only)
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#define STA_W 0x2 // Writeable (non-executable segments)
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#define STA_R 0x2 // Readable (executable segments)
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#define STA_A 0x1 // Accessed
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/* System segment type bits */
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#define STS_T16A 0x1 // Available 16-bit TSS
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#define STS_LDT 0x2 // Local Descriptor Table
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#define STS_T16B 0x3 // Busy 16-bit TSS
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#define STS_CG16 0x4 // 16-bit Call Gate
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#define STS_TG 0x5 // Task Gate / Coum Transmitions
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#define STS_IG16 0x6 // 16-bit Interrupt Gate
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#define STS_TG16 0x7 // 16-bit Trap Gate
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#define STS_T32A 0x9 // Available 32-bit TSS
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#define STS_T32B 0xB // Busy 32-bit TSS
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#define STS_CG32 0xC // 32-bit Call Gate
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#define STS_IG32 0xE // 32-bit Interrupt Gate
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#define STS_TG32 0xF // 32-bit Trap Gate
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#ifdef __ASSEMBLER__
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#define SEG_NULL \
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.word 0, 0; \
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.byte 0, 0, 0, 0
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#define SEG_ASM(type,base,lim) \
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.word (((lim) >> 12) & 0xffff), ((base) & 0xffff); \
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.byte (((base) >> 16) & 0xff), (0x90 | (type)), \
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(0xC0 | (((lim) >> 28) & 0xf)), (((base) >> 24) & 0xff)
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#else /* not __ASSEMBLER__ */
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#include <defs.h>
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/* Gate descriptors for interrupts and traps */
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struct gatedesc {
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unsigned gd_off_15_0 : 16; // low 16 bits of offset in segment
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unsigned gd_ss : 16; // segment selector
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unsigned gd_args : 5; // # args, 0 for interrupt/trap gates
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unsigned gd_rsv1 : 3; // reserved(should be zero I guess)
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unsigned gd_type : 4; // type(STS_{TG,IG32,TG32})
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unsigned gd_s : 1; // must be 0 (system)
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unsigned gd_dpl : 2; // descriptor(meaning new) privilege level
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unsigned gd_p : 1; // Present
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unsigned gd_off_31_16 : 16; // high bits of offset in segment
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};
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/* *
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* Set up a normal interrupt/trap gate descriptor
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* - istrap: 1 for a trap (= exception) gate, 0 for an interrupt gate
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* - sel: Code segment selector for interrupt/trap handler
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* - off: Offset in code segment for interrupt/trap handler
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* - dpl: Descriptor Privilege Level - the privilege level required
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* for software to invoke this interrupt/trap gate explicitly
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* using an int instruction.
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* */
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#define SETGATE(gate, istrap, sel, off, dpl) { \
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(gate).gd_off_15_0 = (uint32_t)(off) & 0xffff; \
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(gate).gd_ss = (sel); \
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(gate).gd_args = 0; \
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(gate).gd_rsv1 = 0; \
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(gate).gd_type = (istrap) ? STS_TG32 : STS_IG32; \
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(gate).gd_s = 0; \
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(gate).gd_dpl = (dpl); \
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(gate).gd_p = 1; \
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(gate).gd_off_31_16 = (uint32_t)(off) >> 16; \
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}
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/* Set up a call gate descriptor */
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#define SETCALLGATE(gate, ss, off, dpl) { \
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(gate).gd_off_15_0 = (uint32_t)(off) & 0xffff; \
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(gate).gd_ss = (ss); \
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(gate).gd_args = 0; \
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(gate).gd_rsv1 = 0; \
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(gate).gd_type = STS_CG32; \
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(gate).gd_s = 0; \
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(gate).gd_dpl = (dpl); \
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(gate).gd_p = 1; \
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(gate).gd_off_31_16 = (uint32_t)(off) >> 16; \
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}
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/* segment descriptors */
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struct segdesc {
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unsigned sd_lim_15_0 : 16; // low bits of segment limit
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unsigned sd_base_15_0 : 16; // low bits of segment base address
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unsigned sd_base_23_16 : 8; // middle bits of segment base address
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unsigned sd_type : 4; // segment type (see STS_ constants)
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unsigned sd_s : 1; // 0 = system, 1 = application
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unsigned sd_dpl : 2; // descriptor Privilege Level
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unsigned sd_p : 1; // present
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unsigned sd_lim_19_16 : 4; // high bits of segment limit
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unsigned sd_avl : 1; // unused (available for software use)
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unsigned sd_rsv1 : 1; // reserved
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unsigned sd_db : 1; // 0 = 16-bit segment, 1 = 32-bit segment
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unsigned sd_g : 1; // granularity: limit scaled by 4K when set
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unsigned sd_base_31_24 : 8; // high bits of segment base address
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};
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#define SEG_NULL \
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(struct segdesc) {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
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#define SEG(type, base, lim, dpl) \
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(struct segdesc) { \
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((lim) >> 12) & 0xffff, (base) & 0xffff, \
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((base) >> 16) & 0xff, type, 1, dpl, 1, \
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(unsigned)(lim) >> 28, 0, 0, 1, 1, \
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(unsigned) (base) >> 24 \
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}
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#define SEGTSS(type, base, lim, dpl) \
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(struct segdesc) { \
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(lim) & 0xffff, (base) & 0xffff, \
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((base) >> 16) & 0xff, type, 0, dpl, 1, \
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(unsigned) (lim) >> 16, 0, 0, 1, 0, \
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(unsigned) (base) >> 24 \
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}
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/* task state segment format (as described by the Pentium architecture book) */
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struct taskstate {
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uint32_t ts_link; // old ts selector
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uintptr_t ts_esp0; // stack pointers and segment selectors
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uint16_t ts_ss0; // after an increase in privilege level
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uint16_t ts_padding1;
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uintptr_t ts_esp1;
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uint16_t ts_ss1;
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uint16_t ts_padding2;
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uintptr_t ts_esp2;
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uint16_t ts_ss2;
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uint16_t ts_padding3;
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uintptr_t ts_cr3; // page directory base
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uintptr_t ts_eip; // saved state from last task switch
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uint32_t ts_eflags;
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uint32_t ts_eax; // more saved state (registers)
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uint32_t ts_ecx;
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uint32_t ts_edx;
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uint32_t ts_ebx;
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uintptr_t ts_esp;
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uintptr_t ts_ebp;
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uint32_t ts_esi;
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uint32_t ts_edi;
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uint16_t ts_es; // even more saved state (segment selectors)
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uint16_t ts_padding4;
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uint16_t ts_cs;
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uint16_t ts_padding5;
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uint16_t ts_ss;
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uint16_t ts_padding6;
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uint16_t ts_ds;
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uint16_t ts_padding7;
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uint16_t ts_fs;
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uint16_t ts_padding8;
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uint16_t ts_gs;
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uint16_t ts_padding9;
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uint16_t ts_ldt;
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uint16_t ts_padding10;
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uint16_t ts_t; // trap on task switch
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uint16_t ts_iomb; // i/o map base address
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} __attribute__((packed));
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#endif /* !__ASSEMBLER__ */
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// A linear address 'la' has a three-part structure as follows:
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//
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// +--------10------+-------10-------+---------12----------+
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// | Page Directory | Page Table | Offset within Page |
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// | Index | Index | |
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// +----------------+----------------+---------------------+
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// \--- PDX(la) --/ \--- PTX(la) --/ \---- PGOFF(la) ----/
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// \----------- PPN(la) -----------/
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//
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// The PDX, PTX, PGOFF, and PPN macros decompose linear addresses as shown.
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// To construct a linear address la from PDX(la), PTX(la), and PGOFF(la),
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// use PGADDR(PDX(la), PTX(la), PGOFF(la)).
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// page directory index
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#define PDX(la) ((((uintptr_t)(la)) >> PDXSHIFT) & 0x3FF)
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// page table index
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#define PTX(la) ((((uintptr_t)(la)) >> PTXSHIFT) & 0x3FF)
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// page number field of address
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#define PPN(la) (((uintptr_t)(la)) >> PTXSHIFT)
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// offset in page
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#define PGOFF(la) (((uintptr_t)(la)) & 0xFFF)
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// construct linear address from indexes and offset
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#define PGADDR(d, t, o) ((uintptr_t)((d) << PDXSHIFT | (t) << PTXSHIFT | (o)))
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// address in page table or page directory entry
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#define PTE_ADDR(pte) ((uintptr_t)(pte) & ~0xFFF)
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#define PDE_ADDR(pde) PTE_ADDR(pde)
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/* page directory and page table constants */
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#define NPDEENTRY 1024 // page directory entries per page directory
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#define NPTEENTRY 1024 // page table entries per page table
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#define PGSIZE 4096 // bytes mapped by a page
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#define PGSHIFT 12 // log2(PGSIZE)
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#define PTSIZE (PGSIZE * NPTEENTRY) // bytes mapped by a page directory entry
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#define PTSHIFT 22 // log2(PTSIZE)
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#define PTXSHIFT 12 // offset of PTX in a linear address
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#define PDXSHIFT 22 // offset of PDX in a linear address
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/* page table/directory entry flags */
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#define PTE_P 0x001 // Present
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#define PTE_W 0x002 // Writeable
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#define PTE_U 0x004 // User
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#define PTE_PWT 0x008 // Write-Through
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#define PTE_PCD 0x010 // Cache-Disable
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#define PTE_A 0x020 // Accessed
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#define PTE_D 0x040 // Dirty
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#define PTE_PS 0x080 // Page Size
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#define PTE_MBZ 0x180 // Bits must be zero
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#define PTE_AVAIL 0xE00 // Available for software use
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// The PTE_AVAIL bits aren't used by the kernel or interpreted by the
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// hardware, so user processes are allowed to set them arbitrarily.
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#define PTE_USER (PTE_U | PTE_W | PTE_P)
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/* Control Register flags */
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#define CR0_PE 0x00000001 // Protection Enable
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#define CR0_MP 0x00000002 // Monitor coProcessor
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#define CR0_EM 0x00000004 // Emulation
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#define CR0_TS 0x00000008 // Task Switched
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#define CR0_ET 0x00000010 // Extension Type
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#define CR0_NE 0x00000020 // Numeric Errror
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#define CR0_WP 0x00010000 // Write Protect
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#define CR0_AM 0x00040000 // Alignment Mask
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#define CR0_NW 0x20000000 // Not Writethrough
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#define CR0_CD 0x40000000 // Cache Disable
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#define CR0_PG 0x80000000 // Paging
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#define CR4_PCE 0x00000100 // Performance counter enable
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#define CR4_MCE 0x00000040 // Machine Check Enable
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#define CR4_PSE 0x00000010 // Page Size Extensions
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#define CR4_DE 0x00000008 // Debugging Extensions
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#define CR4_TSD 0x00000004 // Time Stamp Disable
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#define CR4_PVI 0x00000002 // Protected-Mode Virtual Interrupts
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#define CR4_VME 0x00000001 // V86 Mode Extensions
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#endif /* !__KERN_MM_MMU_H__ */
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