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214 Zeilen
6.3 KiB
214 Zeilen
6.3 KiB
#include <defs.h>
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#include <stdio.h>
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#include <trap.h>
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#include <picirq.h>
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#include <fs.h>
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#include <ide.h>
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#include <x86.h>
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#include <assert.h>
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#define ISA_DATA 0x00
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#define ISA_ERROR 0x01
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#define ISA_PRECOMP 0x01
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#define ISA_CTRL 0x02
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#define ISA_SECCNT 0x02
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#define ISA_SECTOR 0x03
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#define ISA_CYL_LO 0x04
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#define ISA_CYL_HI 0x05
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#define ISA_SDH 0x06
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#define ISA_COMMAND 0x07
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#define ISA_STATUS 0x07
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#define IDE_BSY 0x80
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#define IDE_DRDY 0x40
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#define IDE_DF 0x20
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#define IDE_DRQ 0x08
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#define IDE_ERR 0x01
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#define IDE_CMD_READ 0x20
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#define IDE_CMD_WRITE 0x30
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#define IDE_CMD_IDENTIFY 0xEC
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#define IDE_IDENT_SECTORS 20
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#define IDE_IDENT_MODEL 54
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#define IDE_IDENT_CAPABILITIES 98
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#define IDE_IDENT_CMDSETS 164
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#define IDE_IDENT_MAX_LBA 120
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#define IDE_IDENT_MAX_LBA_EXT 200
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#define IO_BASE0 0x1F0
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#define IO_BASE1 0x170
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#define IO_CTRL0 0x3F4
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#define IO_CTRL1 0x374
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#define MAX_IDE 4
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#define MAX_NSECS 128
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#define MAX_DISK_NSECS 0x10000000U
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#define VALID_IDE(ideno) (((ideno) >= 0) && ((ideno) < MAX_IDE) && (ide_devices[ideno].valid))
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static const struct {
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unsigned short base; // I/O Base
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unsigned short ctrl; // Control Base
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} channels[2] = {
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{IO_BASE0, IO_CTRL0},
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{IO_BASE1, IO_CTRL1},
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};
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#define IO_BASE(ideno) (channels[(ideno) >> 1].base)
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#define IO_CTRL(ideno) (channels[(ideno) >> 1].ctrl)
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static struct ide_device {
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unsigned char valid; // 0 or 1 (If Device Really Exists)
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unsigned int sets; // Commend Sets Supported
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unsigned int size; // Size in Sectors
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unsigned char model[41]; // Model in String
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} ide_devices[MAX_IDE];
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static int
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ide_wait_ready(unsigned short iobase, bool check_error) {
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int r;
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while ((r = inb(iobase + ISA_STATUS)) & IDE_BSY)
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/* nothing */;
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if (check_error && (r & (IDE_DF | IDE_ERR)) != 0) {
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return -1;
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}
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return 0;
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}
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void
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ide_init(void) {
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static_assert((SECTSIZE % 4) == 0);
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unsigned short ideno, iobase;
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for (ideno = 0; ideno < MAX_IDE; ideno ++) {
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/* assume that no device here */
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ide_devices[ideno].valid = 0;
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iobase = IO_BASE(ideno);
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/* wait device ready */
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ide_wait_ready(iobase, 0);
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/* step1: select drive */
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outb(iobase + ISA_SDH, 0xE0 | ((ideno & 1) << 4));
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ide_wait_ready(iobase, 0);
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/* step2: send ATA identify command */
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outb(iobase + ISA_COMMAND, IDE_CMD_IDENTIFY);
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ide_wait_ready(iobase, 0);
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/* step3: polling */
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if (inb(iobase + ISA_STATUS) == 0 || ide_wait_ready(iobase, 1) != 0) {
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continue ;
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}
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/* device is ok */
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ide_devices[ideno].valid = 1;
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/* read identification space of the device */
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unsigned int buffer[128];
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insl(iobase + ISA_DATA, buffer, sizeof(buffer) / sizeof(unsigned int));
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unsigned char *ident = (unsigned char *)buffer;
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unsigned int sectors;
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unsigned int cmdsets = *(unsigned int *)(ident + IDE_IDENT_CMDSETS);
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/* device use 48-bits or 28-bits addressing */
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if (cmdsets & (1 << 26)) {
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sectors = *(unsigned int *)(ident + IDE_IDENT_MAX_LBA_EXT);
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}
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else {
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sectors = *(unsigned int *)(ident + IDE_IDENT_MAX_LBA);
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}
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ide_devices[ideno].sets = cmdsets;
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ide_devices[ideno].size = sectors;
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/* check if supports LBA */
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assert((*(unsigned short *)(ident + IDE_IDENT_CAPABILITIES) & 0x200) != 0);
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unsigned char *model = ide_devices[ideno].model, *data = ident + IDE_IDENT_MODEL;
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unsigned int i, length = 40;
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for (i = 0; i < length; i += 2) {
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model[i] = data[i + 1], model[i + 1] = data[i];
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}
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do {
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model[i] = '\0';
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} while (i -- > 0 && model[i] == ' ');
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cprintf("ide %d: %10u(sectors), '%s'.\n", ideno, ide_devices[ideno].size, ide_devices[ideno].model);
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}
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// enable ide interrupt
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pic_enable(IRQ_IDE1);
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pic_enable(IRQ_IDE2);
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}
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bool
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ide_device_valid(unsigned short ideno) {
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return VALID_IDE(ideno);
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}
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size_t
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ide_device_size(unsigned short ideno) {
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if (ide_device_valid(ideno)) {
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return ide_devices[ideno].size;
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}
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return 0;
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}
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int
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ide_read_secs(unsigned short ideno, uint32_t secno, void *dst, size_t nsecs) {
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assert(nsecs <= MAX_NSECS && VALID_IDE(ideno));
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assert(secno < MAX_DISK_NSECS && secno + nsecs <= MAX_DISK_NSECS);
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unsigned short iobase = IO_BASE(ideno), ioctrl = IO_CTRL(ideno);
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ide_wait_ready(iobase, 0);
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// generate interrupt
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outb(ioctrl + ISA_CTRL, 0);
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outb(iobase + ISA_SECCNT, nsecs);
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outb(iobase + ISA_SECTOR, secno & 0xFF);
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outb(iobase + ISA_CYL_LO, (secno >> 8) & 0xFF);
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outb(iobase + ISA_CYL_HI, (secno >> 16) & 0xFF);
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outb(iobase + ISA_SDH, 0xE0 | ((ideno & 1) << 4) | ((secno >> 24) & 0xF));
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outb(iobase + ISA_COMMAND, IDE_CMD_READ);
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int ret = 0;
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for (; nsecs > 0; nsecs --, dst += SECTSIZE) {
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if ((ret = ide_wait_ready(iobase, 1)) != 0) {
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goto out;
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}
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insl(iobase, dst, SECTSIZE / sizeof(uint32_t));
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}
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out:
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return ret;
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}
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int
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ide_write_secs(unsigned short ideno, uint32_t secno, const void *src, size_t nsecs) {
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assert(nsecs <= MAX_NSECS && VALID_IDE(ideno));
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assert(secno < MAX_DISK_NSECS && secno + nsecs <= MAX_DISK_NSECS);
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unsigned short iobase = IO_BASE(ideno), ioctrl = IO_CTRL(ideno);
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ide_wait_ready(iobase, 0);
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// generate interrupt
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outb(ioctrl + ISA_CTRL, 0);
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outb(iobase + ISA_SECCNT, nsecs);
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outb(iobase + ISA_SECTOR, secno & 0xFF);
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outb(iobase + ISA_CYL_LO, (secno >> 8) & 0xFF);
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outb(iobase + ISA_CYL_HI, (secno >> 16) & 0xFF);
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outb(iobase + ISA_SDH, 0xE0 | ((ideno & 1) << 4) | ((secno >> 24) & 0xF));
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outb(iobase + ISA_COMMAND, IDE_CMD_WRITE);
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int ret = 0;
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for (; nsecs > 0; nsecs --, src += SECTSIZE) {
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if ((ret = ide_wait_ready(iobase, 1)) != 0) {
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goto out;
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}
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outsl(iobase, src, SECTSIZE / sizeof(uint32_t));
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}
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out:
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return ret;
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}
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