《操作系统》的实验代码。

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10 years ago
  1. #ifndef __KERN_MM_MMU_H__
  2. #define __KERN_MM_MMU_H__
  3. /* Eflags register */
  4. #define FL_CF 0x00000001 // Carry Flag
  5. #define FL_PF 0x00000004 // Parity Flag
  6. #define FL_AF 0x00000010 // Auxiliary carry Flag
  7. #define FL_ZF 0x00000040 // Zero Flag
  8. #define FL_SF 0x00000080 // Sign Flag
  9. #define FL_TF 0x00000100 // Trap Flag
  10. #define FL_IF 0x00000200 // Interrupt Flag
  11. #define FL_DF 0x00000400 // Direction Flag
  12. #define FL_OF 0x00000800 // Overflow Flag
  13. #define FL_IOPL_MASK 0x00003000 // I/O Privilege Level bitmask
  14. #define FL_IOPL_0 0x00000000 // IOPL == 0
  15. #define FL_IOPL_1 0x00001000 // IOPL == 1
  16. #define FL_IOPL_2 0x00002000 // IOPL == 2
  17. #define FL_IOPL_3 0x00003000 // IOPL == 3
  18. #define FL_NT 0x00004000 // Nested Task
  19. #define FL_RF 0x00010000 // Resume Flag
  20. #define FL_VM 0x00020000 // Virtual 8086 mode
  21. #define FL_AC 0x00040000 // Alignment Check
  22. #define FL_VIF 0x00080000 // Virtual Interrupt Flag
  23. #define FL_VIP 0x00100000 // Virtual Interrupt Pending
  24. #define FL_ID 0x00200000 // ID flag
  25. /* Application segment type bits */
  26. #define STA_X 0x8 // Executable segment
  27. #define STA_E 0x4 // Expand down (non-executable segments)
  28. #define STA_C 0x4 // Conforming code segment (executable only)
  29. #define STA_W 0x2 // Writeable (non-executable segments)
  30. #define STA_R 0x2 // Readable (executable segments)
  31. #define STA_A 0x1 // Accessed
  32. /* System segment type bits */
  33. #define STS_T16A 0x1 // Available 16-bit TSS
  34. #define STS_LDT 0x2 // Local Descriptor Table
  35. #define STS_T16B 0x3 // Busy 16-bit TSS
  36. #define STS_CG16 0x4 // 16-bit Call Gate
  37. #define STS_TG 0x5 // Task Gate / Coum Transmitions
  38. #define STS_IG16 0x6 // 16-bit Interrupt Gate
  39. #define STS_TG16 0x7 // 16-bit Trap Gate
  40. #define STS_T32A 0x9 // Available 32-bit TSS
  41. #define STS_T32B 0xB // Busy 32-bit TSS
  42. #define STS_CG32 0xC // 32-bit Call Gate
  43. #define STS_IG32 0xE // 32-bit Interrupt Gate
  44. #define STS_TG32 0xF // 32-bit Trap Gate
  45. #ifdef __ASSEMBLER__
  46. #define SEG_NULL \
  47. .word 0, 0; \
  48. .byte 0, 0, 0, 0
  49. #define SEG_ASM(type,base,lim) \
  50. .word (((lim) >> 12) & 0xffff), ((base) & 0xffff); \
  51. .byte (((base) >> 16) & 0xff), (0x90 | (type)), \
  52. (0xC0 | (((lim) >> 28) & 0xf)), (((base) >> 24) & 0xff)
  53. #else /* not __ASSEMBLER__ */
  54. #include <defs.h>
  55. /* Gate descriptors for interrupts and traps */
  56. struct gatedesc {
  57. unsigned gd_off_15_0 : 16; // low 16 bits of offset in segment
  58. unsigned gd_ss : 16; // segment selector
  59. unsigned gd_args : 5; // # args, 0 for interrupt/trap gates
  60. unsigned gd_rsv1 : 3; // reserved(should be zero I guess)
  61. unsigned gd_type : 4; // type(STS_{TG,IG32,TG32})
  62. unsigned gd_s : 1; // must be 0 (system)
  63. unsigned gd_dpl : 2; // descriptor(meaning new) privilege level
  64. unsigned gd_p : 1; // Present
  65. unsigned gd_off_31_16 : 16; // high bits of offset in segment
  66. };
  67. /* *
  68. * Set up a normal interrupt/trap gate descriptor
  69. * - istrap: 1 for a trap (= exception) gate, 0 for an interrupt gate
  70. * - sel: Code segment selector for interrupt/trap handler
  71. * - off: Offset in code segment for interrupt/trap handler
  72. * - dpl: Descriptor Privilege Level - the privilege level required
  73. * for software to invoke this interrupt/trap gate explicitly
  74. * using an int instruction.
  75. * */
  76. #define SETGATE(gate, istrap, sel, off, dpl) { \
  77. (gate).gd_off_15_0 = (uint32_t)(off) & 0xffff; \
  78. (gate).gd_ss = (sel); \
  79. (gate).gd_args = 0; \
  80. (gate).gd_rsv1 = 0; \
  81. (gate).gd_type = (istrap) ? STS_TG32 : STS_IG32; \
  82. (gate).gd_s = 0; \
  83. (gate).gd_dpl = (dpl); \
  84. (gate).gd_p = 1; \
  85. (gate).gd_off_31_16 = (uint32_t)(off) >> 16; \
  86. }
  87. /* Set up a call gate descriptor */
  88. #define SETCALLGATE(gate, ss, off, dpl) { \
  89. (gate).gd_off_15_0 = (uint32_t)(off) & 0xffff; \
  90. (gate).gd_ss = (ss); \
  91. (gate).gd_args = 0; \
  92. (gate).gd_rsv1 = 0; \
  93. (gate).gd_type = STS_CG32; \
  94. (gate).gd_s = 0; \
  95. (gate).gd_dpl = (dpl); \
  96. (gate).gd_p = 1; \
  97. (gate).gd_off_31_16 = (uint32_t)(off) >> 16; \
  98. }
  99. /* segment descriptors */
  100. struct segdesc {
  101. unsigned sd_lim_15_0 : 16; // low bits of segment limit
  102. unsigned sd_base_15_0 : 16; // low bits of segment base address
  103. unsigned sd_base_23_16 : 8; // middle bits of segment base address
  104. unsigned sd_type : 4; // segment type (see STS_ constants)
  105. unsigned sd_s : 1; // 0 = system, 1 = application
  106. unsigned sd_dpl : 2; // descriptor Privilege Level
  107. unsigned sd_p : 1; // present
  108. unsigned sd_lim_19_16 : 4; // high bits of segment limit
  109. unsigned sd_avl : 1; // unused (available for software use)
  110. unsigned sd_rsv1 : 1; // reserved
  111. unsigned sd_db : 1; // 0 = 16-bit segment, 1 = 32-bit segment
  112. unsigned sd_g : 1; // granularity: limit scaled by 4K when set
  113. unsigned sd_base_31_24 : 8; // high bits of segment base address
  114. };
  115. #define SEG_NULL \
  116. (struct segdesc) {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
  117. #define SEG(type, base, lim, dpl) \
  118. (struct segdesc) { \
  119. ((lim) >> 12) & 0xffff, (base) & 0xffff, \
  120. ((base) >> 16) & 0xff, type, 1, dpl, 1, \
  121. (unsigned)(lim) >> 28, 0, 0, 1, 1, \
  122. (unsigned) (base) >> 24 \
  123. }
  124. #define SEGTSS(type, base, lim, dpl) \
  125. (struct segdesc) { \
  126. (lim) & 0xffff, (base) & 0xffff, \
  127. ((base) >> 16) & 0xff, type, 0, dpl, 1, \
  128. (unsigned) (lim) >> 16, 0, 0, 1, 0, \
  129. (unsigned) (base) >> 24 \
  130. }
  131. /* task state segment format (as described by the Pentium architecture book) */
  132. struct taskstate {
  133. uint32_t ts_link; // old ts selector
  134. uintptr_t ts_esp0; // stack pointers and segment selectors
  135. uint16_t ts_ss0; // after an increase in privilege level
  136. uint16_t ts_padding1;
  137. uintptr_t ts_esp1;
  138. uint16_t ts_ss1;
  139. uint16_t ts_padding2;
  140. uintptr_t ts_esp2;
  141. uint16_t ts_ss2;
  142. uint16_t ts_padding3;
  143. uintptr_t ts_cr3; // page directory base
  144. uintptr_t ts_eip; // saved state from last task switch
  145. uint32_t ts_eflags;
  146. uint32_t ts_eax; // more saved state (registers)
  147. uint32_t ts_ecx;
  148. uint32_t ts_edx;
  149. uint32_t ts_ebx;
  150. uintptr_t ts_esp;
  151. uintptr_t ts_ebp;
  152. uint32_t ts_esi;
  153. uint32_t ts_edi;
  154. uint16_t ts_es; // even more saved state (segment selectors)
  155. uint16_t ts_padding4;
  156. uint16_t ts_cs;
  157. uint16_t ts_padding5;
  158. uint16_t ts_ss;
  159. uint16_t ts_padding6;
  160. uint16_t ts_ds;
  161. uint16_t ts_padding7;
  162. uint16_t ts_fs;
  163. uint16_t ts_padding8;
  164. uint16_t ts_gs;
  165. uint16_t ts_padding9;
  166. uint16_t ts_ldt;
  167. uint16_t ts_padding10;
  168. uint16_t ts_t; // trap on task switch
  169. uint16_t ts_iomb; // i/o map base address
  170. } __attribute__((packed));
  171. #endif /* !__ASSEMBLER__ */
  172. // A linear address 'la' has a three-part structure as follows:
  173. //
  174. // +--------10------+-------10-------+---------12----------+
  175. // | Page Directory | Page Table | Offset within Page |
  176. // | Index | Index | |
  177. // +----------------+----------------+---------------------+
  178. // \--- PDX(la) --/ \--- PTX(la) --/ \---- PGOFF(la) ----/
  179. // \----------- PPN(la) -----------/
  180. //
  181. // The PDX, PTX, PGOFF, and PPN macros decompose linear addresses as shown.
  182. // To construct a linear address la from PDX(la), PTX(la), and PGOFF(la),
  183. // use PGADDR(PDX(la), PTX(la), PGOFF(la)).
  184. // page directory index
  185. #define PDX(la) ((((uintptr_t)(la)) >> PDXSHIFT) & 0x3FF)
  186. // page table index
  187. #define PTX(la) ((((uintptr_t)(la)) >> PTXSHIFT) & 0x3FF)
  188. // page number field of address
  189. #define PPN(la) (((uintptr_t)(la)) >> PTXSHIFT)
  190. // offset in page
  191. #define PGOFF(la) (((uintptr_t)(la)) & 0xFFF)
  192. // construct linear address from indexes and offset
  193. #define PGADDR(d, t, o) ((uintptr_t)((d) << PDXSHIFT | (t) << PTXSHIFT | (o)))
  194. // address in page table or page directory entry
  195. #define PTE_ADDR(pte) ((uintptr_t)(pte) & ~0xFFF)
  196. #define PDE_ADDR(pde) PTE_ADDR(pde)
  197. /* page directory and page table constants */
  198. #define NPDEENTRY 1024 // page directory entries per page directory
  199. #define NPTEENTRY 1024 // page table entries per page table
  200. #define PGSIZE 4096 // bytes mapped by a page
  201. #define PGSHIFT 12 // log2(PGSIZE)
  202. #define PTSIZE (PGSIZE * NPTEENTRY) // bytes mapped by a page directory entry
  203. #define PTSHIFT 22 // log2(PTSIZE)
  204. #define PTXSHIFT 12 // offset of PTX in a linear address
  205. #define PDXSHIFT 22 // offset of PDX in a linear address
  206. /* page table/directory entry flags */
  207. #define PTE_P 0x001 // Present
  208. #define PTE_W 0x002 // Writeable
  209. #define PTE_U 0x004 // User
  210. #define PTE_PWT 0x008 // Write-Through
  211. #define PTE_PCD 0x010 // Cache-Disable
  212. #define PTE_A 0x020 // Accessed
  213. #define PTE_D 0x040 // Dirty
  214. #define PTE_PS 0x080 // Page Size
  215. #define PTE_MBZ 0x180 // Bits must be zero
  216. #define PTE_AVAIL 0xE00 // Available for software use
  217. // The PTE_AVAIL bits aren't used by the kernel or interpreted by the
  218. // hardware, so user processes are allowed to set them arbitrarily.
  219. #define PTE_USER (PTE_U | PTE_W | PTE_P)
  220. /* Control Register flags */
  221. #define CR0_PE 0x00000001 // Protection Enable
  222. #define CR0_MP 0x00000002 // Monitor coProcessor
  223. #define CR0_EM 0x00000004 // Emulation
  224. #define CR0_TS 0x00000008 // Task Switched
  225. #define CR0_ET 0x00000010 // Extension Type
  226. #define CR0_NE 0x00000020 // Numeric Errror
  227. #define CR0_WP 0x00010000 // Write Protect
  228. #define CR0_AM 0x00040000 // Alignment Mask
  229. #define CR0_NW 0x20000000 // Not Writethrough
  230. #define CR0_CD 0x40000000 // Cache Disable
  231. #define CR0_PG 0x80000000 // Paging
  232. #define CR4_PCE 0x00000100 // Performance counter enable
  233. #define CR4_MCE 0x00000040 // Machine Check Enable
  234. #define CR4_PSE 0x00000010 // Page Size Extensions
  235. #define CR4_DE 0x00000008 // Debugging Extensions
  236. #define CR4_TSD 0x00000004 // Time Stamp Disable
  237. #define CR4_PVI 0x00000002 // Protected-Mode Virtual Interrupts
  238. #define CR4_VME 0x00000001 // V86 Mode Extensions
  239. #endif /* !__KERN_MM_MMU_H__ */