《操作系统》的实验代码。
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12 years ago
  1. #ifndef __KERN_MM_MMU_H__
  2. #define __KERN_MM_MMU_H__
  3. /* Eflags register */
  4. #define FL_CF 0x00000001 // Carry Flag
  5. #define FL_PF 0x00000004 // Parity Flag
  6. #define FL_AF 0x00000010 // Auxiliary carry Flag
  7. #define FL_ZF 0x00000040 // Zero Flag
  8. #define FL_SF 0x00000080 // Sign Flag
  9. #define FL_TF 0x00000100 // Trap Flag
  10. #define FL_IF 0x00000200 // Interrupt Flag
  11. #define FL_DF 0x00000400 // Direction Flag
  12. #define FL_OF 0x00000800 // Overflow Flag
  13. #define FL_IOPL_MASK 0x00003000 // I/O Privilege Level bitmask
  14. #define FL_IOPL_0 0x00000000 // IOPL == 0
  15. #define FL_IOPL_1 0x00001000 // IOPL == 1
  16. #define FL_IOPL_2 0x00002000 // IOPL == 2
  17. #define FL_IOPL_3 0x00003000 // IOPL == 3
  18. #define FL_NT 0x00004000 // Nested Task
  19. #define FL_RF 0x00010000 // Resume Flag
  20. #define FL_VM 0x00020000 // Virtual 8086 mode
  21. #define FL_AC 0x00040000 // Alignment Check
  22. #define FL_VIF 0x00080000 // Virtual Interrupt Flag
  23. #define FL_VIP 0x00100000 // Virtual Interrupt Pending
  24. #define FL_ID 0x00200000 // ID flag
  25. /* Application segment type bits */
  26. #define STA_X 0x8 // Executable segment
  27. #define STA_E 0x4 // Expand down (non-executable segments)
  28. #define STA_C 0x4 // Conforming code segment (executable only)
  29. #define STA_W 0x2 // Writeable (non-executable segments)
  30. #define STA_R 0x2 // Readable (executable segments)
  31. #define STA_A 0x1 // Accessed
  32. /* System segment type bits */
  33. #define STS_T16A 0x1 // Available 16-bit TSS
  34. #define STS_LDT 0x2 // Local Descriptor Table
  35. #define STS_T16B 0x3 // Busy 16-bit TSS
  36. #define STS_CG16 0x4 // 16-bit Call Gate
  37. #define STS_TG 0x5 // Task Gate / Coum Transmitions
  38. #define STS_IG16 0x6 // 16-bit Interrupt Gate
  39. #define STS_TG16 0x7 // 16-bit Trap Gate
  40. #define STS_T32A 0x9 // Available 32-bit TSS
  41. #define STS_T32B 0xB // Busy 32-bit TSS
  42. #define STS_CG32 0xC // 32-bit Call Gate
  43. #define STS_IG32 0xE // 32-bit Interrupt Gate
  44. #define STS_TG32 0xF // 32-bit Trap Gate
  45. /* Gate descriptors for interrupts and traps */
  46. struct gatedesc {
  47. unsigned gd_off_15_0 : 16; // low 16 bits of offset in segment
  48. unsigned gd_ss : 16; // segment selector
  49. unsigned gd_args : 5; // # args, 0 for interrupt/trap gates
  50. unsigned gd_rsv1 : 3; // reserved(should be zero I guess)
  51. unsigned gd_type : 4; // type(STS_{TG,IG32,TG32})
  52. unsigned gd_s : 1; // must be 0 (system)
  53. unsigned gd_dpl : 2; // descriptor(meaning new) privilege level
  54. unsigned gd_p : 1; // Present
  55. unsigned gd_off_31_16 : 16; // high bits of offset in segment
  56. };
  57. /* *
  58. * Set up a normal interrupt/trap gate descriptor
  59. * - istrap: 1 for a trap (= exception) gate, 0 for an interrupt gate
  60. * - sel: Code segment selector for interrupt/trap handler
  61. * - off: Offset in code segment for interrupt/trap handler
  62. * - dpl: Descriptor Privilege Level - the privilege level required
  63. * for software to invoke this interrupt/trap gate explicitly
  64. * using an int instruction.
  65. * */
  66. #define SETGATE(gate, istrap, sel, off, dpl) { \
  67. (gate).gd_off_15_0 = (uint32_t)(off) & 0xffff; \
  68. (gate).gd_ss = (sel); \
  69. (gate).gd_args = 0; \
  70. (gate).gd_rsv1 = 0; \
  71. (gate).gd_type = (istrap) ? STS_TG32 : STS_IG32; \
  72. (gate).gd_s = 0; \
  73. (gate).gd_dpl = (dpl); \
  74. (gate).gd_p = 1; \
  75. (gate).gd_off_31_16 = (uint32_t)(off) >> 16; \
  76. }
  77. /* Set up a call gate descriptor */
  78. #define SETCALLGATE(gate, ss, off, dpl) { \
  79. (gate).gd_off_15_0 = (uint32_t)(off) & 0xffff; \
  80. (gate).gd_ss = (ss); \
  81. (gate).gd_args = 0; \
  82. (gate).gd_rsv1 = 0; \
  83. (gate).gd_type = STS_CG32; \
  84. (gate).gd_s = 0; \
  85. (gate).gd_dpl = (dpl); \
  86. (gate).gd_p = 1; \
  87. (gate).gd_off_31_16 = (uint32_t)(off) >> 16; \
  88. }
  89. /* segment descriptors */
  90. struct segdesc {
  91. unsigned sd_lim_15_0 : 16; // low bits of segment limit
  92. unsigned sd_base_15_0 : 16; // low bits of segment base address
  93. unsigned sd_base_23_16 : 8; // middle bits of segment base address
  94. unsigned sd_type : 4; // segment type (see STS_ constants)
  95. unsigned sd_s : 1; // 0 = system, 1 = application
  96. unsigned sd_dpl : 2; // descriptor Privilege Level
  97. unsigned sd_p : 1; // present
  98. unsigned sd_lim_19_16 : 4; // high bits of segment limit
  99. unsigned sd_avl : 1; // unused (available for software use)
  100. unsigned sd_rsv1 : 1; // reserved
  101. unsigned sd_db : 1; // 0 = 16-bit segment, 1 = 32-bit segment
  102. unsigned sd_g : 1; // granularity: limit scaled by 4K when set
  103. unsigned sd_base_31_24 : 8; // high bits of segment base address
  104. };
  105. #define SEG_NULL \
  106. (struct segdesc){0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
  107. #define SEG(type, base, lim, dpl) \
  108. (struct segdesc){ \
  109. ((lim) >> 12) & 0xffff, (base) & 0xffff, \
  110. ((base) >> 16) & 0xff, type, 1, dpl, 1, \
  111. (unsigned)(lim) >> 28, 0, 0, 1, 1, \
  112. (unsigned) (base) >> 24 \
  113. }
  114. #define SEG16(type, base, lim, dpl) \
  115. (struct segdesc){ \
  116. (lim) & 0xffff, (base) & 0xffff, \
  117. ((base) >> 16) & 0xff, type, 1, dpl, 1, \
  118. (unsigned) (lim) >> 16, 0, 0, 1, 0, \
  119. (unsigned) (base) >> 24 \
  120. }
  121. /* task state segment format (as described by the Pentium architecture book) */
  122. struct taskstate {
  123. uint32_t ts_link; // old ts selector
  124. uintptr_t ts_esp0; // stack pointers and segment selectors
  125. uint16_t ts_ss0; // after an increase in privilege level
  126. uint16_t ts_padding1;
  127. uintptr_t ts_esp1;
  128. uint16_t ts_ss1;
  129. uint16_t ts_padding2;
  130. uintptr_t ts_esp2;
  131. uint16_t ts_ss2;
  132. uint16_t ts_padding3;
  133. uintptr_t ts_cr3; // page directory base
  134. uintptr_t ts_eip; // saved state from last task switch
  135. uint32_t ts_eflags;
  136. uint32_t ts_eax; // more saved state (registers)
  137. uint32_t ts_ecx;
  138. uint32_t ts_edx;
  139. uint32_t ts_ebx;
  140. uintptr_t ts_esp;
  141. uintptr_t ts_ebp;
  142. uint32_t ts_esi;
  143. uint32_t ts_edi;
  144. uint16_t ts_es; // even more saved state (segment selectors)
  145. uint16_t ts_padding4;
  146. uint16_t ts_cs;
  147. uint16_t ts_padding5;
  148. uint16_t ts_ss;
  149. uint16_t ts_padding6;
  150. uint16_t ts_ds;
  151. uint16_t ts_padding7;
  152. uint16_t ts_fs;
  153. uint16_t ts_padding8;
  154. uint16_t ts_gs;
  155. uint16_t ts_padding9;
  156. uint16_t ts_ldt;
  157. uint16_t ts_padding10;
  158. uint16_t ts_t; // trap on task switch
  159. uint16_t ts_iomb; // i/o map base address
  160. };
  161. #endif /* !__KERN_MM_MMU_H__ */